1. Field of the Invention
The present invention generally relates to a method of manufacturing integrated circuit devices on semiconductor substrates. More specifically, the present invention relates to a processing method for fabricating devices having a substantially equal etched polysilicon gate width in regions of an integrated circuit having different device densities.
2. Description of the Related Art
Polysilicon gate lengths are highly important for transistor scaling in a semiconductor device. Short-channel effects significantly alter the dc drive current--drain source voltage (I.sub.D -V.sub.DS) characteristics of long-channel MOSFETs that are operated in inversion. In one aspect, the combined effects of a reduced gate length (a reduced channel length) result in a change in threshold voltage V.sub.T. In addition, the mobility of carriers in the channel are reduced by a "mobility-degradation factor" resulting from the gate field and a "velocity-saturation factor" due to the lateral channel field. The mobility-degradation factor and the velocity-saturation factor combine to reduce the drain current I.sub.D Furthermore, the channel length is modulated by the drain voltage when the device is in saturation, causing an increase in the drain current saturation voltage I.sub.DSAT with an increasing drain source voltage V.sub.DS. The ultimate result of these variations affect drain current I.sub.D or source-to-drain current I.sub.SD that are caused by short-channel effects is a reduced integrated circuit speed performance and increased sensitivity to variations in gate length and other device parameters.
The performance of an integrated circuit depends not only on the value of the channel lengths but also upon the uniformity of the channel lengths across an integrated circuit. In an integrated circuit having some devices with relatively longer channel lengths and other devices with relatively shorter channel lengths, the devices with a shorter channel length have a higher effective drain current I.sub.D than devices with longer channel lengths. These differences in effective drain current I.sub.D in a integrated circuit create problems associated with hot carrier injection (HCI).
Hot carrier injection results as device dimensions are reduced while the supply voltage remains the same or the supply voltage is reduced but reduced more slowly than the device dimensions so that the lateral electric field in the device channel increases. The increase in lateral electric field causes inversion layer charges to be accelerated to be accelerated to cause various harmful device phenomena, called hot-carrier effects. A highly important hot-carrier effect is damage inflicted to the gate oxide or the silicon(Si)-oxide(SiO.sub.2) interface.
To avoid these harmful hot-carrier effects, the drive current must be limited. By limiting the drive current to devices with a shorter channel length to a suitable level to avoid hot-carrier effect problems, the drive current is also limited to devices with a longer channel length, thereby reducing the speed of the devices. The speed of an integrated circuit is optimized while reducing damage relating to hot-carrier effects by fabricating devices which have a substantially equal channel length.
What is needed is a technique for fabricating an integrated circuit that forms devices having a substantially uniform device channel length.